Mill Computing, Inc. Forums The Mill Architecture Metadata Reply To: Metadata

Ryan Hitchman
Post count: 3

None/NaR are neat ideas. The demonstration of them working together with the vector operations to make high-performance strcpy simple is very impressive. Using NaRs to delay faulting until it becomes an externally observable effect is particularly clever, and None closely mirrors a compiler’s reasoning about undefined behavior.

Allowing arithmetic operations to have truncate/fault/saturate/widen semantics in combination with type-tagged data should make vector assembly more readable, assuming it includes type comments. Not having penalties for moving vectors between ALU and FPU units will be useful.

1. How are FPU rounding modes handled? A single control register? Encoded in each instruction? (I’m guessing control register)

2. Is casting a belt item a 0-cycle flow-side operation? If I start with a vector of 4-byte elements {0, 1, NaR, 2} and try to cast it to a vector of 8-byte elements, do I get {0x100000000, NaR}, or a fault?

NaRs might cause strange behavior if there’s a long-running loop that generates a NaR in an early iteration and carries it forward but doesn’t “retire” it until after exiting the loop. Compilers should detect this case and insert an explicit NaR check when faults might retire a long time after occurring.

I hope the belt timings work out when the hardware starts being finalized. There’s a lot of flow-side operations going on that border on magical (vector pick??).

cypherpunks: Intel CPUs since Sandy Bridge have also had constant-latency FPU operations.