Mill Computing, Inc. Forums The Mill Architecture Single register Reply To: Single register

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How does this interact with decoding?

Way back in lecture #1, Ivan went on at some length about the importance of simple decoding for high IPC. The Mill doesn’t waste space like fixed-width VLIW, but each of two instruction streams has decoding pipelined so each pipeline stage presents the stream to an array of decoders. The unused slots are later nullified,

(Using the standard Mill nomenclature, “instructions” are executed one per cycle and are made up of a number of parallel “operations” which are similar to instructions on (super)scalar CPUs.)

The important thing is that operations are fixed size. It’s only their variable number that makes the number of instruction bits decoded this stage variable.

However, I keep hearing about these variadic call/retn/rescue/inner/leave operations, and now compressed versions of those based on bitmaps. Doesn’t that break fixed-size operations?

One thing I can think of is that if this is the only operation decoded in this stream this phase, then a variable-sized operand list would work. If there is no following operation to be decoded this phase, then it’s okay/ Basically, the operation gets presented to an array of operand decoders, and the unused ones are nullified.

But lecture 6 (@28:00) clearly says that one instructions can contain multiple call operations.

How can this work?