Mill Computing, Inc. Forums The Mill Architecture Memory Reply To: Memory

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I’m a digital logic designer but not a processor designer. Possibly na├»ve questions follow.

1. At 44:35 in the video: when the retire stations monitor stores and see a match, why do they rerequest the load? Can’t they grab that outbound data instead of requesting what just flew by?

2. At 1:13:00: more of a general cache eviction question. Instead of waiting until an eviction is forced, can some *small* number of LRU lines be proactively pushed downward BUT still kept in cache, such that if a cache line is needed, one of those LRU lines would be instantaneously available? This would likely require an extra bit per line to indicate that it’s mirrored at the next level away.