Mill Computing, Inc. › Forums › The Mill › Architecture › Memory › Reply To: Memory

Ivan Godard
Keymaster
August 12, 2014 at 10:56 pm
Post count: 689
#1348

There are no RMW ops. The Mill uses optimistic concurrency using the top level cache for the write set, much like the IBM and Intel optimistic facility. It’s been mentioned somewhere, but I don’t remember if it was in the talks or here, or maybe comp.arch.