Mill Computing, Inc. Forums The Mill Architecture Specification Reply To: Specification

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After watching the specification talk, I got the impression that a key parameter of the Mill’s architecture, namely the bit-width of pointers (64, with 4 bits reserved) was not a free parameter, but is a “hardwired” part of the Arch. Are pointer width (and the number of reserved address bits) hardwired, or are those both parameters that I managed not to see in the specification?

64-bit wide pointers makes sense for general-purpose computing and for competing on the high end. However in the higher end of the embedded CPU world (e.g. 32-bit ARM and MIPS based chips), which has large and increasing volume, 64-bit wide pointers would hurt code density, especially for processors with all their memory on chip. Even with 4 bits of a pointer reserved, as in the Mill as shown in the presentations, 2^28 bytes of address space would dwarf the memory on such chips, and will for quite some time. (Right now, on-chip memories in such chips are typically a megabyte or less.) Is a 32-bit Mill completely out of the question, or is it eventually possible, but simply a very low priority?