Mill Computing, Inc

White Papers

Mon, 15 Jan 2018 18:11:48 +0000

Switches

Thu, 06 Jul 2017 03:50:22 +0000

Forum Topic: Switches

Talk by Ivan Godard - July 12, 2017, at the

SFBay Association of C/C++ Users

Slides: mill-cpu-switches.04 (.pptx)

This is the eleventh topic publicly presented related to the Mill general-purpose CPU architecture.

Multi-way branches, known as switches or case clauses in various languages, are a notorious pain for compiler writers and CPU architects. On the critical path in important applications from lexers to byte-code interpreters, switches often suffer from poor branch prediction performance. Short switches with few cases can use a chain of ifs but are hampered by the low rate at which branches issue on conventional hardware and may miss several times while working down the chain. A common alternative is to indirect-branch through a jump table, but that approach is subject to misses in the data cache as well a prediction miss. Some CPU architectures have taken the approach of putting the table in instruction space, but that adds expensive shifters and datapaths to the instruction fetch.

Patents

Thu, 27 Oct 2016 04:25:24 +0000

U.S. Patent 9,513,920 - Computer Processor Employing Split-Stream Encoding

This patent is for the split-stream method of encoding that permits Mill CPUs to decode extremely wide instructions (those with many independent operations in each instruction) using a compact and flexible variable-length encoding that is also fast to decode. The stream of instructions that is the program being executed is split into two streams of half-instructions that are stored separately in memory but are processed in lock-step by the CPU decoder. Because wide fixed length instruction encodings use an impractical amount of cache and memory, and variable-length encodings take time polynomial in the width, instruction decode on legacy CPUs is limited to eight operations per cycle or fewer; Mill split-stream encoding supports instruction widths of over thirty operations decoded per cycle. In addition, split-stream permits doubling the amount of instruction cache with no clock or pipeline penalty.

Threading

Tue, 05 May 2015 22:19:20 +0000

Forum Topic: Threading

Talk by Ivan Godard - December 5, 2017, at Facebook

Slides: threading.02(.pptx)

This is the thirteenth topic publicly presented on the Mill general-purpose CPU architecture. It covers the methods used to manage threads on the Mill Architecture. The talk assumes some general familiarity with software threads.

Inter-process Communication

Tue, 05 May 2015 22:17:25 +0000

Forum Topic: Inter-process Communication

Talk by Ivan Godard - October 4, 2017, at the

Silicon Valley Linux Users Group

Slides: 2017-10-04-IPC.4 (.pptx)

This was the twelfth topic publicly presented related to the Mill general-purpose CPU architecture. It covers Inter-Process Communication for the Mill CPU architecture family. The talk assumes a familiarity with aspects of CPU architecture in general and C++ programming in particular.

Wide Data

Tue, 05 May 2015 22:15:32 +0000

The Mill is a new general-purpose CPU architectural family. The talk will present machine-level details of the Mill support for bigger-than-scalar data.

Most modern architectures have SIMD operations that work on vectors of data, in addition to the scalars used by all CPUs. Typically there is a limited assortment of vector operations, working on data of a limited set of element sizes, and often a limited set of sizes for the whole vector. To make matters worse for the programmer, the operands and element sizes available frequently vary with the whole-vector size, and succeeding models of the “same” architecture rarely offer the same vector facilities. As a result, vector codes must usually be written in assembler, and special-cased for each version of the target CPU.

The Compiler

Tue, 05 May 2015 22:12:36 +0000

Forum Topic: The Compiler

Talk by Ivan Godard - June 10, 2015, at the SFBay Association of C/C++ Users

NOTE: the slides require genuine Microsoft PowerPoint to view; open source PowerPoint clones are unable to show the animations, which are essential to the slide content. If you do not have access to PowerPoint then watch the video, which shows the slides as intended.

General Questions

Fri, 28 Mar 2014 04:03:02 +0000

Q: What does NYF stand for? Stands for Not Yet Filed - as used here it refers to a patent or patents that are Not Yet Filed. Questions about patentable mechanisms that are NYF cannot be answered without an NDA due to USPTO rules.

Q: Why no PDF slides? Publishing PDF slides (instead of .pptx) would make them available to more people. A: Unfortunately PDF format doesn’t support the animations, and without those the slides are pretty useless. We looked into creating a completely different presentation without the animations, but decided we don’t have the bandwidth, and the need for a static format was better served by white papers, of which we have a few in process. We had been using OpenOffice (and tried LibreOffice) but found both useless because of bugs in the animation on some platforms and the generally limited support for animation creation, and so settled on MSOffice as the best of the choices.

Pipelining

Mon, 24 Mar 2014 03:16:39 +0000

Forum Topic: Pipelining

Talk by Ivan Godard – 2014-07-14 at Facebook

Security

Sat, 15 Feb 2014 02:15:54 +0000

Forum Topic: Security

Talk given by Ivan Godard - 2014-03-21 at Google.

Introduction to the Mill CPU Programming Model

Fri, 07 Feb 2014 10:48:53 +0000

The Mill is a new CPU architecture designed for very high single-thread performance within a very small power envelope.

The Mill has a 10x single-thread power/performance gain over conventional out-of-order (OoO) superscalar architectures, yet runs the same programs without rewrite.

The Mill is an extremely-wide-issue, statically scheduled design with exposed pipeline. High-end Mills can decode, issue, and execute over thirty MIMD operations per cycle, each cycle.

The Mill architecture is able to pipeline and vectorise almost all loops, including while loops and loops containing calls and flow control.

Execution

Sun, 29 Dec 2013 07:45:26 +0000

Forum Topic: Execution

Talk by Ivan Godard - 2014-02-05 at Stanford University’s Computer Systems Colloquium (EE380).

Specification

Wed, 18 Dec 2013 23:46:11 +0000

Forum Topic: Specification

Talk by Ivan Godard – 2014-05-14 at the SFBay Association of C/C++ Users

Metadata

Wed, 18 Dec 2013 23:13:19 +0000

Forum Topic: Metadata

Talk by Ivan Godard – 2013-12-11 at the SFBay Association of C/C++ Users

Prediction

Wed, 18 Dec 2013 23:02:04 +0000

Forum Topic: Prediction

Talk by Ivan Godard – 2013-11-12 at IEEE CS Santa Clara Valley

Memory

Wed, 18 Dec 2013 22:48:19 +0000

Forum Topic: Memory

Talk by Ivan Godard – 2013-10-16 at Stanford

The Belt

Wed, 18 Dec 2013 22:38:14 +0000

Forum Topic: The Belt

Talk by Ivan Godard – 2013-07-11 at Google

Instruction Encoding

Mon, 16 Dec 2013 05:58:13 +0000

Forum Topic: Instruction Encoding

White paper – 2013-08-23

White paper: mill_cpu_split-stream_encoding (.PDF)

The Mill: Split-stream encoding

Real-world programs often thrash in the instruction cache, especially when SMT methods are used. The Mill™ split-stream encoding doubles the effective capacity of the instruction cache at no increase in per-instruction power usage or cache access latency, while also sharply increasing the potential maximal decode rate for instruction sets that use variable-length encoding.

in the press

Mon, 16 Dec 2013 04:52:07 +0000

Mentions of the Mill, Mill Computing and Out-of-the-Box Computing in the press.

Mill Computing heads to FPGA demo, seeks funds
January 12, 2017 - eeNews Europe

EE Times Silicon 60: Hot Startups to Watch
September 8, 2015 - EE Times

EE Times Silicon 60: Hot Startups to Watch
July 15, 2014 - EE Times

Startup Seeks Funds to Realize ‘Belt’ Processor
December 16, 2013 - Electronics360

Mill CPU: Stack Machines Instead of Turing
December 9, 2013 - EE Times