Vector ops

I am patiently waiting for Wide Data talk, but in the meantime I have few questions.

How Mill vector ops ideas compare to AVX2, AVX512, and ARM SVE?

I think ability to write the genAsm in style of ARM SVE would be absolutely awesome. With specializer either converting to fixed widest vectors available in hardware or into variable vectors in style of SVE (and hardware operating on widest vectors with things like strides and widths being exposed as ops that can be used to update indexes, loops, at runtime, etc). I think it also nicely fits in into a concept of polymorphic ops that Mill supports via metadata.

I really like AVX512 and SVE, because of their masking features, how they are similar to concept of NaRs, but also conflict detection, reduce operations (horizontal add/min/max/abs-add, and possibly mul, these can be emulated as log/add/exp probably in many cases, if numbers are positive), conditional loads, blends, and bitwise ternary operations (that can implement a 3-bit LUTs to implement a lot of vector logic) and explicit per-op rounding modes. Intel, ARM and Fujitsu really pushed what code can be vectorized with these new features. (Both by hand and by autovectorizer).

I hope you are aware of the benefits (especially AVX512 and SVE parts), and make Mill competitive.

https://github.com/WebAssembly/simd is another piece that is really worth contributing to, because this might be a huge platform for a lot of SIMD computations in the future. Currently it is driven a lot by Intel tho, and Chrome/Firefox that focus on x86. It would be very sad to see this standard be tightly locked to x86 or ARM NEON.