Questions about feasibility of some concepts

Some time ago, while watching videos of Dr. Godard’s lecture series, a few ideas cam to mind relating to both possible technologies and potential applications which could be used in conjunction with the Mill, and I was hoping someone here could answer some questions about the technical feasibility of these concepts.

Before I go on, I am aware that what I am going to ask about is all at the ‘brainstorming’ level at this stage, and frankly, I have no idea whether it will lead anywhere at all. I am expecting most of the answers to be along the lines of ‘been there, done that’, or ‘that used to be a standard process but got superseded years ago’, or ‘it was tried back in xxxx, but they never could get it working’, or even ‘you would think that would be possible, but…’. Please bear with me for my ignorance on these topics; I am asking as much because I am wondering why these haven’t been done before (or whether they have or not), as they all seem fairly obvious combinations of existing technologies.

Also, these are ideas which are for long-term planning rather than regarding the immediate future of the Mill. I am mainly floating them now because I didn’t want to forget them later.

The basic set of ideas is that of a small-footprint SoC with a single-core CPU a conventional DRAM or SRAM memory, and an additional NVRAM memory, within a single EMR-hardened packaging. Related to this is the idea of a cut-off fusing system on the package pin-outs within the IC package itself, which could cut the packaging off in the case of an external electrical surge. Finally, I wanted to discuss the possiblity of incorporating a miniature lithium-ion battery (or a graphene supercap, or – if it proves a workable system – the new solid-state amorphous lithium battery now in development) within the packaging as well, to provide emergency shutdown power for the processor.

(Another thought I have had, which I doubt would be feasible, would be whether there exists a thin-film form of a thermoelectric junction which could be incorporated into the packaging – or, again, even into the die itself – with the heat receiver lead going out of the package to a suitable heat exchanger. The idea is that the heat could be channeled off of one or seven several IC packages to a physically separate heat sink and cooling unit, eliminating the need to attach heat sinks to the chip packages externally. I suspect that this is more an idle fantasy than a practical idea, but it might solve a lot of the issues involved in thermal buildup.)

The purpose of this is as a new class of mostly self-contained processors for aerospace systems, to provide both high-performance avionics, and high-durability storage of performance logs (including possibly serving as a next-generation FDR/CVR system with better survivability than current black boxes, and at a lowered cost, weight, and power consumption, possibly allowing for added redundancy).

As I said, this relates directly to Dr. Godard’s lectures. At several points in the lectures I watched, he mentioned that the business model for Mill would require them to start off in niche market with relatively small production runs, due to the need to build up their production capacity over time (even if they partnered with an existing IC fabricator for the production). Embedded systems were specifically mentioned a likely targets for their early markets, especially ones which required very high performance but very low power consumption. I believe that avionics was specifically mentioned.

This collided with my own thoughts about avionics, and specifically, of a television show entitled Air Crash Investigation which I have been fond of watching. The series details the process of accident investigation and reconstruction, including the process of recovering and collecting data stored in the Flight Data Recorder and Cockpit Voice Recorder.

The importance of these data recorders – and especially the need for them to have extreme survivability in order for it to be usable – led me to consider the possibility of pairing a non-volatile memory with a suitable CPU (such as the Mill is intended to be) in a highly radiation hardened, heat resistant, and physical-shock resistant package. My reasoning was that the more self-contained the unit could be, and the better the isolation it could have in the case of a catastrophic failure of the craft (air or space) and/or the equipment it is connected to, the more likely it would be to survive.

This seemed to me like the ideal initial market for the Mill. However, I do not have enough of a background in the technology to judge how feasible it was, and if it was, what it would take to bring it to the point of being a salable product. However, it occurred to me that the data recorders themselves were mostly passive – they really didn’t need a high-performance processor. However, the avionics often do, and this design would likely provide high reliability in operation as well as high survivability in a failure scenario – the processors could be produced for the avionics, and the black boxes would then be a secondary market in the same customer space.

The non-volatile memory is a key component to this design, as it would allow safety and accident investigators to scrutinize the memory or the individual processor packages even if the black boxes were not recovered or inoperable. The chip or package would be arranged so that the DRAM could be evicted or duplicated to the NVRAM for the parts of the software and data that need to persist. This would allow the entire CPU to be self-contained, save for the I/O to the devices it is connected to, and allow a persistent OS to run without ever needing a separate secondary storage.

It would also provide redundancy to the data storage – while a central FDR/CVR pair would still been needed, each SoC would be able to store its own portion of the critical data, allowing at least part of the results to be recovered even if the black boxes themselves weren’t found or were unusable.

Needless to say, the memory and persistent storage would be drastically constrained compared to a consumer-grade system, but for an embedded system running a highly-tuned RTOS and a mostly-fixed hardware management programs (drivers etc), this should not be a great sacrifice.

For this purpose, I envision using something along the lines of either 3D XPoint, if the necessary IP agreements could be reached with Intel, or MRAM, if similar agreements could be reached with Everspin. However, I am not very clear on many aspects of either of those technologies, and I am aware that while Everspin would probably more approachable, the MRAM technology has serious flaws in comparison to 3d Xpoint, primarily in regards to cell density due to crosstalk between the cells (their current process only gets a maximum density of 130nm). However, from what little I have managed to learn, it is more promising in regards to the specific design I have in mind.

Can anyone give me an feedback on this? As I said, I am assuming that this is not a new set of ideas, and I would be interested in hear what, if anything, had or could be done with them.

• This topic was modified 7 years, 4 months ago by  Schol-R-LEA.
• This topic was modified 7 years, 4 months ago by  Schol-R-LEA.