f2sdz
From Mill Computing Wiki
speculable exu stream exu block compute phase operation in the decimal floating point value domain using modulo overflow behavior that produces condition codes and rounds toward zero
Inexactly convert a decimal floating point value to a signed integer, rounding toward zero and normal modulo overflow.
operands: like Addd [dd:d]
Core | In Slots | Latencies |
---|---|---|
Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable