Difference between revisions of "Instruction Set/mulfn"

From Mill Computing Wiki
Jump to: navigation, search
Line 15:Line 15:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Silver/Encoding#578|Silver]] || E0 E1 || w,w:w=4 wv,wv:wv=4 d,d:d=5 dv,dv:dv=5 q,q:q=6 qv,qv:qv=6  
+
| [[Cores/Silver/Encoding#mulfn|Silver]] || E0 E1 || w,w:w=4 wv,wv:wv=4 d,d:d=5 dv,dv:dv=5 q,q:q=6 qv,qv:qv=6  
 
|-
 
|-
| [[Cores/Gold/Encoding#578|Gold]] || E0 E1 E2 E3 || w,w:w=4 wv,wv:wv=4 d,d:d=5 dv,dv:dv=5 q,q:q=6 qv,qv:qv=6  
+
| [[Cores/Gold/Encoding#mulfn|Gold]] || E0 E1 E2 E3 || w,w:w=4 wv,wv:wv=4 d,d:d=5 dv,dv:dv=5 q,q:q=6 qv,qv:qv=6  
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain   that produces condition codes

native on: Silver Gold

Floating point multplication in current rounding to nearest.


mulfn(f x, f y) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 w,w:w=4 wv,wv:wv=4 d,d:d=5 dv,dv:dv=5 q,q:q=6 qv,qv:qv=6
Gold E0 E1 E2 E3 w,w:w=4 wv,wv:wv=4 d,d:d=5 dv,dv:dv=5 q,q:q=6 qv,qv:qv=6


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable