Difference between revisions of "Instruction Set/integerdz"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:integerdz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bl...")
 
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Decimal8/Encoding#469|Decimal8]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
+
| [[Cores/Decimal8/Encoding#integerdz|Decimal8]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
|-
 
|-
| [[Cores/Decimal16/Encoding#469|Decimal16]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
+
| [[Cores/Decimal16/Encoding#integerdz|Decimal16]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   that produces condition codes

native on: Decimal8 Decimal16

round to integral-valued float


integerdz(d x) → d r0

operands: like Addd [dd:d]


Core In Slots Latencies
Decimal8 E0 E1 d:d=4 dv:dv=4 q:q=5 qv:qv=5
Decimal16 E0 E1 d:d=4 dv:dv=4 q:q=5 qv:qv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable