Difference between revisions of "Instruction Set/f2ufixp"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:f2ufixp}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">speculable  exu stream Decode|exu blo...")
 
m (Protected "Instruction Set/f2ufixp": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
(No difference)

Latest revision as of 14:11, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   using excepting overflow behavior   that produces condition codes and rounds toward positive infinity

native on: Silver

convert float to unsigned integer


f2ufixp(f op0) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable