Difference between revisions of "Instruction Set/f2ueffz"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:f2ueffz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu bloc...") |
(No difference) |
Revision as of 06:56, 2 October 2014
realizing exu stream exu block compute phase operation in the binary floating point value domain using modulo overflow behavior that produces condition codes
convert float to unsigned integer
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Gold | E0 E1 E2 E3 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
