Difference between revisions of "Instruction Set/divu"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Silver/Encoding#divu|Silver]] || E0 || b,b:b=6 bv,bv:bv=6 h,h:h=6 hv,hv:hv=8 w,w:w=6 wv,wv:wv=8 d,d:d=6 dv,dv:dv=8 q,q:q=6 qv,qv:qv=8
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| [[Cores/Silver/Encoding#divu|Silver]] || E0 ||  
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Silver/Encoding#divu|Silver]] || E0 || b,b:b=6 bv,bv:bv=6 h,h:h=6 hv,hv:hv=8 w,w:w=6 wv,wv:wv=8 d,d:d=6 dv,dv:dv=8 q,q:q=6 qv,qv:qv=8
+
| [[Cores/Silver/Encoding#divu|Silver]] || E0 ||  
 
|}
 
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:09, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   that produces condition codes

native on: Silver

Unsigned integer division for quotient.

related operations: remu, divRemu, rdivu, rootu, rrootu


divu(u x, u y) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Silver E0

divu(u x, imm y) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Silver E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable