Difference between revisions of "Instruction Set/clear"

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(Created page with "{{DISPLAYTITLE:clear}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|exu block]...")
 
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bit reset
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Clear a single indexed bit.
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**related operations:** [[Instruction_Set/set|set], [[Instruction_Set/test|test]
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<code style="font-size:130%"><b style="color:#050">clear</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bit</span></i>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">clear</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bit</span></i>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>

Revision as of 18:48, 26 November 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Clear a single indexed bit.

    • related operations:** [[Instruction_Set/set|set], [[Instruction_Set/test|test]

clear(op x, bit bit) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

clear(op x, op bit) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1