Difference between revisions of "Instruction Set/brs"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:brs}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream [[Decode|flow block]...")
 
m (Protected "Instruction Set/brs": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
(No difference)

Latest revision as of 14:08, 23 February 2021

realizing  flow stream  flow block  transfer phase   operation  

native on: all

branch


brs(op op0, ops args)

operands: like Inv :


encoding: brs(op count0, off op0, count off0) , brs(op count0, off op0, count lit0, lit off0) , brs(op count0, off op0, count lit0, lit lit1, lit off0)

Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 F1 F2 1
Gold F0 1

brs(lbl off0, ops args)

operands: like Inv :


encoding: brs(off count0, count off0) , brs(off count0, count lit0, lit off0) , brs(off count0, count lit0, lit lit1, lit off0) , brs(off count0, count lit0, lit lit1, lit lit2, lit off0)

Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 F1 F2 1
Gold F0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable