Difference between revisions of "Instruction Set/alternate"
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| − | + | Interlace two Vectors. | |
| + | i.e. take two vectors [a b c d] and [1 2 3 4] and produce two vectors [a 1 b 2] and [c 3 d 4]. | ||
| + | The actual number of vector elements is dependent on the scalar domain width and the vector operand width of the specific core. | ||
| + | |||
| + | <b>related operations:</b> [[Instruction_Set/shuffle|shuffle]], [[Instruction_Set/vec|vec]], [[Instruction_Set/inject|inject]], [[Instruction_Set/extract|extract]] | ||
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---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">alternate</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v1</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v2</span>) → [[Domains#op|op]] r<sub>0</sub>, [[Domains#op|op]] r<sub>1</sub></code> | <code style="font-size:130%"><b style="color:#050">alternate</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v1</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v2</span>) → [[Domains#op|op]] r<sub>0</sub>, [[Domains#op|op]] r<sub>1</sub></code> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#alternate|Tin]] || E0 || 2 2 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#alternate|Copper]] || E0 E1 || 2 2 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#alternate|Silver]] || E0 E1 E2 E3 || 2 2 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#alternate|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#alternate|Decimal8]] || E0 E1 E2 E3 || 2 2 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#alternate|Decimal16]] || E0 E1 E2 E3 || 2 2 |
|} | |} | ||
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| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 02:36, 16 December 2014
Interlace two Vectors. i.e. take two vectors [a b c d] and [1 2 3 4] and produce two vectors [a 1 b 2] and [c 3 d 4]. The actual number of vector elements is dependent on the scalar domain width and the vector operand width of the specific core.
related operations: shuffle, vec, inject, extract
alternate(op v1, op v2) → op r0, op r1
operands: like Alternate XX:XX
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 E1 | 2 2 |
| Silver | E0 E1 E2 E3 | 2 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
| Decimal8 | E0 E1 E2 E3 | 2 2 |
| Decimal16 | E0 E1 E2 E3 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
