Difference between revisions of "Instruction Set/addsx"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#200|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#addsx|Tin]] || E0 || 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#200|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#addsx|Copper]] || E0 E1 || 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#200|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#addsx|Silver]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#200|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#addsx|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#200|Decimal8]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal8/Encoding#addsx|Decimal8]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#200|Decimal16]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal16/Encoding#addsx|Decimal16]] || E0 E1 E2 E3 || 2
 
|}
 
|}
  
Line 39:Line 39:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#201|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#addsx|Tin]] || E0 || 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#201|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#addsx|Copper]] || E0 E1 || 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#201|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#addsx|Silver]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#201|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#addsx|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#201|Decimal8]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal8/Encoding#addsx|Decimal8]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#201|Decimal16]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal16/Encoding#addsx|Decimal16]] || E0 E1 E2 E3 || 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using excepting overflow behavior   that produces condition codes

aliases: addsxv
native on: all

Excepting signed integer add. Overflow or underflow produces a NaR.

addsx(s x, s y) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2

addsx(s x, imm y) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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