shiftlsw
From Mill Computing Wiki
speculable exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
Signed bitwise left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get sign extended in the widening.
shiftlsw(s x, bit bits) → s r0
operands: like Widening xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 | |
| Gold | E0 |
operands: like Widening xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 | |
| Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
