narrowfz
From Mill Computing Wiki
realizing exu stream exu block compute phase operation in the binary floating point value domain and rounds toward zero
native on: Silver
Half the width of a binary float value. Rounding towards zero.
Can produce the IEEE 754 16bit binary float interchange format.
This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.
operands: like Narrowvf [FF:½F]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 |
narrowfz(f op0, width width0) → f r0
operands: like Narrowf [ff:½f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
