divRemu
From Mill Computing Wiki
speculable exu stream exu block compute phase operation in the unsigned integer value domain that produces condition codes
native on: Silver
Unsigned integer division for quotient and remainder.
related operations: divu, remu, rdivu, rootu, rrootu
divRemu(u x, u y) → u r0, u r1
operands: like DivRem [xx:xx]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 | b,b:b,b=6,6 bv,bv:bv,bv=6,6 h,h:h,h=6,6 hv,hv:hv,hv=6,6 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=8,8 dv,dv:dv,dv=8,8 q,q:q,q=8,8 qv,qv:qv,qv=8,8 |
divRemu(u x, imm y) → u r0, u r1
operands: like DivRem [xx:xx]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 | b,b:b,b=6,6 bv,bv:bv,bv=6,6 h,h:h,h=6,6 hv,hv:hv,hv=6,6 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=8,8 dv,dv:dv,dv=8,8 q,q:q,q=8,8 qv,qv:qv,qv=8,8 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
