adduwv
From Mill Computing Wiki
speculable exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
Widening unsigned integer vector addition. If any of the result values in the vector overflows, the vector is widened as with widenuv.
operands: like Widenv XX:2X2X
| Core | In Slots | [▸] Latencies |
|---|
adduwv(u x, imm y) → u r0, u r1
operands: like Widenv XX:2X2X
| Core | In Slots | [▸] Latencies |
|---|
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
