shiftlswv

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Signed bitwise vector left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get sign extended in the widening. Produces two result vectors.

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shiftlswv(s x, bit bits) → s r0, s r1

operands: like Widenv XX:2X2X

Core	In Slots	Latencies
Tin	E0	2 2
Copper	E0	2 2
Silver	E0 E1	2 2
Gold	E0 E1	2 2
Decimal8	E0 E1	2 2
Decimal16	E0 E1	2 2

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shiftlswv(s x, n bits) → s r0, s r1

operands: like Widenv XX:2X2X

Core	In Slots	Latencies
Tin	E0	2 2
Copper	E0	2 2
Silver	E0 E1	2 2
Gold	E0 E1	2 2
Decimal8	E0 E1	2 2
Decimal16	E0 E1	2 2

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