alternate

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Interlace two Vectors. i.e. take two vectors [a b c d] and [1 2 3 4] and produce two vectors [a 1 b 2] and [c 3 d 4]. The actual number of vector elements is dependent on the scalar domain width and the vector operand width of the specific core.

related operations: shuffle, vec, inject, extract

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alternate(op v1, op v2) → op r0, op r1

operands: like Alternate XX:XX

Core	In Slots	Latencies
Tin	E0	2 2
Copper	E0 E1	2 2
Silver	E0 E1 E2 E3	2 2
Gold	E0 E1 E2 E3 E4 E5 E6 E7	2 2
Decimal8	E0 E1 E2 E3	2 2
Decimal16	E0 E1 E2 E3	2 2

Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable