shiftluwv

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realizing exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes

native on: all

bitwise shift

shiftluwv(u x, bit bits) → u r₀, u r₁

operands: like Widenv XX:2X2X

Core	In Slots	Latencies
Tin	E0	2 2
Copper	E0	2 2
Silver	E0 E1	2 2
Gold	E0 E1	2 2
Decimal8	E0 E1	2 2
Decimal16	E0 E1	2 2

shiftluwv(u x, n bits) → u r₀, u r₁

operands: like Widenv XX:2X2X

Core	In Slots	Latencies
Tin	E0	2 2
Copper	E0	2 2
Silver	E0 E1	2 2
Gold	E0 E1	2 2
Decimal8	E0 E1	2 2
Decimal16	E0 E1	2 2

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