mulsw

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

multiplication

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mulsw(s x, s y) → s r0

operands: like Widen xx:2x

Core	In Slots	Latencies
Tin	E0	b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Copper	E0	b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Silver	E0 E1	b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Gold	E0 E1 E2 E3	b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Decimal8	E0 E1	b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Decimal16	E0 E1	b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6

Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable