negsw

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realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

negate

negsw(s x) → s r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b:h=1 h:w=1 w:d=2 d:q=2
Copper E0 E1 b:h=1 h:w=1 w:d=2 d:q=2
Silver E0 E1 E2 E3 b:h=1 h:w=1 w:d=2 d:q=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 b:h=1 h:w=1 w:d=2 d:q=2
Decimal8 E0 E1 E2 E3 b:h=1 h:w=1 w:d=2 d:q=2
Decimal16 E0 E1 E2 E3 b:h=1 h:w=1 w:d=2 d:q=2
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