f2uedxp
From Mill Computing Wiki
realizing exu stream exu block compute phase operation in the decimal floating point value domain using excepting overflow behavior that produces condition codes
Exactly convert a decimal floating point value to a unsigned integer, rounding toward positive infinity and producing NaRs on overflow.
operands: like Addd [dd:d]
Core | In Slots | Latencies |
---|---|---|
Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |