br
From Mill Computing Wiki
Conditionless branch. There must always be exactly one conditionless branch or return operation in every EBB, and always in last position. There can be several conditionless branches in an EBB and even in the same operation, which are all processes in parallel, but the first successful in the lowest slot wins.
The targets in branches, whether literal or from a belt operand, are always relative to the EBB entry point. The optional delay serves to synchronize with operations that need to finish before control is transferred to the next EBB.
related operations: brtr, brfl
br(p target)
operands: like Inv :
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
operands: like Inv :
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
br(lbl target)
operands: like Inv :
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
operands: like Inv :
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
