shiftruffz
From Mill Computing Wiki
speculable exu stream exu block compute phase operation in the unsigned fixed point value domain that produces condition codes and rounds to nearest, ties away from zero
native on: all
Unsigned fixed point shift right. Rounds towards nearest away from zero. When shifting fixed point values to the right the least significant bit can be treated differently according to the same different rounding strategies that apply to floating point values as well.
shiftruffz(uf x, bit bits) → uf r0
operands: like Shift [xi:x]
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
Copper | E0 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
Silver | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
Gold | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
Decimal8 | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
Decimal16 | E0 E1 | b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2 |
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