widensv

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain  

native on: all

Double the scalar widths in an signed integer vector.

Sign extends the upper half.

The natively available byte widths on all Cores are 1, 2, 4, 8, and on the high end also 16.

Vector widen operations always produce two result vectors to accomodate the widening of maximum size vectors. The first result vector then contains the widened values of the lower half elements of the operand, and the second result the upper elements.

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widensv(s v) → s r0, s r1

operands: like Widenv XX:2X2X

Core	In Slots	Latencies
Tin	E0	2 2
Copper	E0 E1	2 2
Silver	E0 E1 E2 E3	2 2
Gold	E0 E1 E2 E3 E4 E5 E6 E7	2 2
Decimal8	E0 E1 E2 E3	2 2
Decimal16	E0 E1 E2 E3	2 2

Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable