mulswv

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Signed integer multiply. Widening for a vector.

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mulswv(s x, s y) → s r0, s r1

operands: like Widenv XX:2X2X

Core	In Slots	Latencies
Tin	E0	bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Copper	E0	bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Silver	E0 E1	bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Gold	E0 E1 E2 E3	bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Decimal8	E0 E1	bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Decimal16	E0 E1	bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6

Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable