wr

realizing  exu stream  writer block  writer phase   operation   in the logical value domain  

native on: all

hardware writer

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wr(scratch dst, op v)

operands: like NoResult [xx]:

Core	In Slots	[▸]  Latencies
Tin	W0 W1	3
Copper	W0 W1	3
Silver	W0 W1 W2 W3 W4	3
Gold	W0 W1 W2 W3 W4	3
Decimal8	W0 W1 W2 W3 W4	3
Decimal16	W0 W1 W2 W3 W4	3

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wr(reg dst, op v)

operands: like NoResult [xx]:

Core	In Slots	[▸]  Latencies
Tin	W0 W1	3
Copper	W0 W1	3
Silver	W0 W1 W2 W3 W4	3
Gold	W0 W1 W2 W3 W4	3
Decimal8	W0 W1 W2 W3 W4	3
Decimal16	W0 W1 W2 W3 W4	3

---

wr(stream dst, op v)

operands: like NoResult [xx]:

Core	In Slots	[▸]  Latencies
Tin	W0 W1	3
Copper	W0 W1	3
Silver	W0 W1 W2 W3 W4	3
Gold	W0 W1 W2 W3 W4	3
Decimal8	W0 W1 W2 W3 W4	3
Decimal16	W0 W1 W2 W3 W4	3

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