Difference between revisions of "Instruction Set/s2fdfz"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:s2fdfz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu block...") |
(No difference) |
Revision as of 06:59, 2 October 2014
realizing exu stream exu block compute phase operation in the decimal floating point value domain that produces condition codes
convert signed integer to float
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
