Difference between revisions of "Instruction Set/negswv"
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Revision as of 06:59, 2 October 2014
realizing exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
negate
operands: like Widenv XX:2X2X
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | 2 2 |
Copper | E0 E1 | 2 2 |
Silver | E0 E1 E2 E3 | 2 2 |
Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
Decimal8 | E0 E1 E2 E3 | 2 2 |
Decimal16 | E0 E1 E2 E3 | 2 2 |