Difference between revisions of "Instruction Set/addffz"
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Revision as of 06:57, 2 October 2014
realizing exu stream exu block compute phase operation in the binary floating point value domain that produces condition codes
addition
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5 |
| Gold | E0 E1 E2 E3 | w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5 |
