Difference between revisions of "Instruction Set/fmadfz"

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Revision as of 06:56, 2 October 2014

realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain  

native on: Decimal8 Decimal16

fused multiply-add or -add/subtract

fmadfz(d x, d y, d z) → d r0

operands: like Addd [dd:d]


encoding: fmadfz(d x) , exuArgs(op arg0, op arg1)

Core In Slots [▸]  Latencies
Decimal8 E0 E1 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8
Decimal16 E0 E1 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8

fmadfz(d x, d y, d z, d w) → d r0, d r1

operands: like Fmasd [dd:d]


encoding: fmadfz(d x, d y) , exuArgs(op arg0, op arg1)

Core In Slots [▸]  Latencies
Decimal8 E0 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8
Decimal16 E0 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8
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