Difference between revisions of "Instruction Set/alternate"

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Revision as of 06:56, 2 October 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

interlace two vectors

alternate(op v1, op v2) → op r0, op r1

operands: like Alternate XX:XX


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2
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