Difference between revisions of "Cores"

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m (Protected "Cores": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
Line 4:Line 4:
  
 
{| class="wikitable"
 
{| class="wikitable"
! !! Belt!! Scalar!! Vector!! Pipelines!! Retire Stations!! Scratchpad!! Spiller Buffers/Stack!! iCache Line!! float!! decimal
+
! !! Belt!! Scalar!! Vector!! Pipelines!! Retire Stations!! Scratchpad!! Spiller Buffers/Stack!! Exu-side Cache Line!! Flow-side Cache Line!! float!! decimal
 
|-
 
|-
 
|<b>[[Cores/Tin|Tin]]</b>
 
|<b>[[Cores/Tin|Tin]]</b>
|style="text-align:right"|8
+
|&#10004;|8
|style="text-align:right"|64bit
+
|&#10004;|64bit
|style="text-align:right"|8B
+
|&#10004;|8B
|style="text-align:right"|13
+
|&#10004;|19
|style="text-align:right"|8
+
|&#10004;|8
|style="text-align:right"|128B
+
|&#10004;|4096B
|style="text-align:right"|8/16MB
+
|&#10004;|8/16MB
 +
|&#10004;|16B
 
|style="text-align:right"|16B
 
|style="text-align:right"|16B
|style="text-align:center"|&#10008;
+
|style="text-align:right"|&#10004;
|style="text-align:center"|&#10008;
+
 
|-
 
|-
 
|slots
 
|slots
Line 22:Line 22:
 
|-
 
|-
 
|<b>[[Cores/Copper|Copper]]</b>
 
|<b>[[Cores/Copper|Copper]]</b>
|style="text-align:right"|8
+
|&#10004;|8
|style="text-align:right"|64bit
+
|&#10004;|64bit
|style="text-align:right"|8B
+
|&#10004;|8B
|style="text-align:right"|13
+
|&#10004;|19
|style="text-align:right"|8
+
|&#10004;|8
|style="text-align:right"|128B
+
|&#10004;|8192B
|style="text-align:right"|8/16MB
+
|&#10004;|8/16MB
 +
|&#10004;|16B
 
|style="text-align:right"|16B
 
|style="text-align:right"|16B
|style="text-align:center"|&#10008;
+
|style="text-align:right"|&#10004;
|style="text-align:center"|&#10008;
+
 
|-
 
|-
 
|slots
 
|slots
Line 37:Line 37:
 
|-
 
|-
 
|<b>[[Cores/Silver|Silver]]</b>
 
|<b>[[Cores/Silver|Silver]]</b>
|style="text-align:right"|16
+
|&#10004;|16
|style="text-align:right"|64bit
+
|&#10004;|64bit
|style="text-align:right"|16B
+
|&#10004;|16B
|style="text-align:right"|25
+
|&#10004;|34
|style="text-align:right"|16
+
|&#10004;|16
|style="text-align:right"|256B
+
|&#10004;|8192B
|style="text-align:right"|16/256MB
+
|&#10004;|16/256MB
 +
|&#10004;|64B
 
|style="text-align:right"|32B
 
|style="text-align:right"|32B
|style="text-align:center"|&#10004;
+
|style="text-align:right"|&#10004;
|style="text-align:center"|&#10008;
+
 
|-
 
|-
 
|slots
 
|slots
|colspan="10"| reader: 6&nbsp;&nbsp; writer: 5&nbsp;&nbsp; pick: 2&nbsp;&nbsp; exu: 4&nbsp;&nbsp; flow: 4&nbsp;&nbsp;
+
|colspan="10"| reader: 4&nbsp;&nbsp; writer: 5&nbsp;&nbsp; pick: 2&nbsp;&nbsp; exu: 4&nbsp;&nbsp; flow: 4&nbsp;&nbsp;
 
|-
 
|-
 
|<b>[[Cores/Gold|Gold]]</b>
 
|<b>[[Cores/Gold|Gold]]</b>
|style="text-align:right"|32
+
|&#10004;|32
|style="text-align:right"|128bit
+
|&#10004;|128bit
|style="text-align:right"|32B
+
|&#10004;|16B
|style="text-align:right"|37
+
|&#10004;|19
|style="text-align:right"|16
+
|&#10004;|16
|style="text-align:right"|512B
+
|&#10004;|16384B
|style="text-align:right"|16/256MB
+
|&#10004;|16/256MB
|style="text-align:right"|64B
+
|&#10004;|32B
|style="text-align:center"|&#10004;
+
|style="text-align:center"|&#10008;
+
|-
+
|slots
+
|colspan="10"| reader: 8&nbsp;&nbsp; writer: 5&nbsp;&nbsp; pick: 4&nbsp;&nbsp; exu: 8&nbsp;&nbsp; flow: 8&nbsp;&nbsp;
+
|-
+
|<b>[[Cores/Decimal8|Decimal8]]</b>
+
|style="text-align:right"|16
+
|style="text-align:right"|64bit
+
|style="text-align:right"|8B
+
|style="text-align:right"|25
+
|style="text-align:right"|16
+
|style="text-align:right"|256B
+
|style="text-align:right"|16/256MB
+
|style="text-align:right"|32B
+
|style="text-align:center"|&#10008;
+
|style="text-align:center"|&#10004;
+
|-
+
|slots
+
|colspan="10"| reader: 6&nbsp;&nbsp; writer: 5&nbsp;&nbsp; pick: 2&nbsp;&nbsp; exu: 4&nbsp;&nbsp; flow: 4&nbsp;&nbsp;
+
|-
+
|<b>[[Cores/Decimal16|Decimal16]]</b>
+
|style="text-align:right"|16
+
|style="text-align:right"|64bit
+
 
|style="text-align:right"|16B
 
|style="text-align:right"|16B
|style="text-align:right"|25
+
|style="text-align:right"|&#10004;
|style="text-align:right"|16
+
|style="text-align:right"|256B
+
|style="text-align:right"|16/256MB
+
|style="text-align:right"|32B
+
|style="text-align:center"|&#10008;
+
|style="text-align:center"|&#10004;
+
 
|-
 
|-
 
|slots
 
|slots
|colspan="10"| reader: 6&nbsp;&nbsp; writer: 5&nbsp;&nbsp; pick: 2&nbsp;&nbsp; exu: 4&nbsp;&nbsp; flow: 4&nbsp;&nbsp;
+
|colspan="10"| reader: 2&nbsp;&nbsp; writer: 2&nbsp;&nbsp; pick: 1&nbsp;&nbsp; exu: 2&nbsp;&nbsp; flow: 2&nbsp;&nbsp;
 
|}
 
|}

Latest revision as of 13:24, 23 February 2021

The Mill Architecture describes a family of processor cores so that each family member can serve its own unique set of requirements and work loads. For the time being all defined Mill cores are purely simulated and cover a pretty generalistic range of profiles.

The difference between Tin and Copper may not be apparent from this table, but the second exu and flow Slots on Tin are reduced to an absolute minimum and don't even contain any ALU or branch Functional Units respectively.

Belt Scalar Vector Pipelines Retire Stations Scratchpad Spiller Buffers/Stack Exu-side Cache Line Flow-side Cache Line float decimal
Tin864bit8B1984096B8/16MB16B16B
slots reader: 2   writer: 2   pick: 1   exu: 2   flow: 2  
Copper864bit8B1988192B8/16MB16B16B
slots reader: 2   writer: 2   pick: 1   exu: 2   flow: 2  
Silver1664bit16B34168192B16/256MB64B32B
slots reader: 4   writer: 5   pick: 2   exu: 4   flow: 4  
Gold32128bit16B191616384B16/256MB32B16B
slots reader: 2   writer: 2   pick: 1   exu: 2   flow: 2