Difference between revisions of "Instruction Set/widenv"
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{{DISPLAYTITLE:widenv}} | {{DISPLAYTITLE:widenv}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the logical value domain]] <br /> |
'''aliases:''' widenuv <br /> | '''aliases:''' widenuv <br /> | ||
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
Latest revision as of 09:31, 9 February 2015
speculable exu stream exu block compute phase operation in the logical value domain
aliases: widenuv
native on: all
Double the scalar widths in an unsigned integer vector.
Zero extends the upper half.
The natively available byte widths on all Cores are 1, 2, 4, 8, and on the high end also 16.
Vector widen operations always produce two result vectors to accomodate the widening of maximum size vectors. The first result vector then contains the widened values of the lower half of the operand, and the second result the upper.
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 E1 | 2 2 |
| Silver | E0 E1 E2 E3 | 2 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
| Decimal8 | E0 E1 E2 E3 | 2 2 |
| Decimal16 | E0 E1 E2 E3 | 2 2 |
widenv(op v1, op v2) → op r0, op r1
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 E1 | 2 2 |
| Silver | E0 E1 E2 E3 | 2 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
| Decimal8 | E0 E1 E2 E3 | 2 2 |
| Decimal16 | E0 E1 E2 E3 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
