Difference between revisions of "Instruction Set/f2sedsn"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:f2sedsn}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bloc...")
(No difference)

Revision as of 06:56, 2 October 2014

realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   using saturating overflow behavior   that produces condition codes

native on: Decimal8 Decimal16

convert float to signed integer


f2sedsn(d x) → d r0

operands: like Addd [dd:d]


Core In Slots Latencies
Decimal8 E0 E1 d:d=4 dv:dv=4 q:q=5 qv:qv=5
Decimal16 E0 E1 d:d=4 dv:dv=4 q:q=5 qv:qv=5