Difference between revisions of "Instruction Set/leqdx"

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m (Protected "Instruction Set/leqdx": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
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{{DISPLAYTITLE:leqdx}}
 
{{DISPLAYTITLE:leqdx}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
</div>
 
</div>

Revision as of 09:26, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the decimal floating point value domain  

native on: Decimal8 Decimal16

Decimal float lesser than or equal comparison. NaN-Aware. When one or both of the operands are a NaN, the comparison is false.

related operations: leqd


leqdx(d x, d y) → d r0

operands: like Addd [dd:d]


Core In Slots Latencies
Decimal8 E0 E1 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
Decimal16 E0 E1 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable