Difference between revisions of "Instruction Set/shiftluw"
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{{DISPLAYTITLE:shiftluw}} | {{DISPLAYTITLE:shiftluw}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the unsigned integer value domain]] [[Overflow|using widening overflow behavior]] [[Condition Code|that produces condition codes]]<br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
Revision as of 09:24, 9 February 2015
speculable exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
Unsigned bitwise left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get zero extended in the widening.
shiftluw(u x, bit bits) → u r0
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 1 |
| Copper | E0 | 1 |
| Silver | E0 E1 | 1 |
| Gold | E0 E1 | 1 |
| Decimal8 | E0 E1 | 1 |
| Decimal16 | E0 E1 | 1 |
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 1 |
| Copper | E0 | 1 |
| Silver | E0 E1 | 1 |
| Gold | E0 E1 | 1 |
| Decimal8 | E0 E1 | 1 |
| Decimal16 | E0 E1 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
