Difference between revisions of "Instruction Set/subswv"

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m (Protected "Instruction Set/subswv": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
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subtraction
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Widening signed integer vector subtraction.
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If any of the result values in the vector overflows, the vector is widened as with [[Instruction_Set/widenuv|widenuv]].
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<code style="font-size:130%"><b style="color:#050">subswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code>
 
<code style="font-size:130%"><b style="color:#050">subswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code>

Revision as of 10:39, 11 January 2015

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Widening signed integer vector subtraction. If any of the result values in the vector overflows, the vector is widened as with widenuv.


subswv(s x, s y) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2

subswv(s x, imm y) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable