Difference between revisions of "Instruction Set/u2swv"
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m (Protected "Instruction Set/u2swv": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite))) | |||
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| − | + | Unsigned integer vector to signed integer vectors. Widening. | |
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<code style="font-size:130%"><b style="color:#050">u2swv</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#op|op]] r<sub>0</sub>, [[Domains#op|op]] r<sub>1</sub></code> | <code style="font-size:130%"><b style="color:#050">u2swv</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#op|op]] r<sub>0</sub>, [[Domains#op|op]] r<sub>1</sub></code> | ||
Revision as of 10:39, 11 January 2015
realizing exu stream exu block compute phase operation in the logical value domain using widening overflow behavior
native on: all
Unsigned integer vector to signed integer vectors. Widening.
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 E1 | 2 2 |
| Silver | E0 E1 E2 E3 | 2 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
| Decimal8 | E0 E1 E2 E3 | 2 2 |
| Decimal16 | E0 E1 E2 E3 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
