Difference between revisions of "Instruction Set/widen"
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| − | + | Double the scalar width of an unsigned integer. | |
| + | |||
| + | Zero extends the upper half. | ||
| + | |||
| + | The natively available byte widths on all [[Cores]] are 1, 2, 4, 8, and on the high end also 16. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">widen</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v</span>) → [[Domains#op|op]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">widen</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">v</span>) → [[Domains#op|op]] r<sub>0</sub></code> | ||
Revision as of 10:38, 11 January 2015
realizing exu stream exu block compute phase operation in the logical value domain
aliases: widenu
native on: all
Double the scalar width of an unsigned integer.
Zero extends the upper half.
The natively available byte widths on all Cores are 1, 2, 4, 8, and on the high end also 16.
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 1 |
| Copper | E0 E1 | 1 |
| Silver | E0 E1 E2 E3 | 1 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 1 |
| Decimal8 | E0 E1 E2 E3 | 1 |
| Decimal16 | E0 E1 E2 E3 | 1 |
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 1 |
| Copper | E0 E1 | 1 |
| Silver | E0 E1 E2 E3 | 1 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 1 |
| Decimal8 | E0 E1 E2 E3 | 1 |
| Decimal16 | E0 E1 E2 E3 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
