Difference between revisions of "Instruction Set/s2ffn"
From Mill Computing Wiki
m (Protected "Instruction Set/s2ffn": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite))) | |||
| Line 4: | Line 4: | ||
</div> | </div> | ||
| − | + | Signed integer to binary float conversion. Rounding towards negative infinity. | |
| + | |||
| + | |||
| + | |||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">s2ffn</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">s2ffn</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | ||
Revision as of 10:37, 11 January 2015
realizing exu stream exu block compute phase operation in the binary floating point value domain that produces condition codes and rounds toward negative infinity
Signed integer to binary float conversion. Rounding towards negative infinity.
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Gold | E0 E1 E2 E3 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
