Difference between revisions of "Instruction Set/s2fdz"
From Mill Computing Wiki
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| − | + | Signed integer to decimal float conversion. Rounding towards zero. | |
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<code style="font-size:130%"><b style="color:#050">s2fdz</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#d|d]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">s2fdz</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#d|d]] r<sub>0</sub></code> | ||
Revision as of 10:33, 11 January 2015
realizing exu stream exu block compute phase operation in the decimal floating point value domain that produces condition codes and rounds toward zero
Signed integer to decimal float conversion. Rounding towards zero.
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
