Difference between revisions of "Cores/Tin"
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Revision as of 01:36, 3 January 2015
Cores: Tin Copper Silver Gold Decimal8 Decimal16
Tin is the smallest viable general purpose chip. It only has each one properly populated exu and flow slot, so instruction level parallelism is quite limited. It also doesn't support wider vector operands. It is extremely low power though, so it would lend itself to ultra-mobile devices or it could serve as an overblown micro controller.
Belt: 8 Morsel: 3bit Scalar Width: 64bit Operand Maximum Size: 8B
Pipelines: 13 Retire Stations: 8 Scratchpad: 128B
Spill Buffers: 8 Spiller Stack Size: 16MB
iCache Line: 16B
2 reader slots, 9bits wide 2 writer slots, 6bits wide 1 pick slots, 10bits wide
exu slot 0, 18bits wide, with functional units: alu count mul nope shift shuffle
exu slot 1, 7bits wide, with functional units: cc exuArgs
flow slot 0, 15bits wide, with functional units: cache con conform control ls misc nopf
flow slot 1, 9bits wide, with functional units: con flowArgs
