Difference between revisions of "Instruction Set/brfl"
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Branch on false predicate. | Branch on false predicate. | ||
| − | There can be several conditionless branches in an [[EBB]] and even in the same operation, which are all | + | There can be several conditionless branches in an [[EBB]] and even in the same operation, which are all processed in parallel, but the first successful in the lowest slot wins. |
The targets in branches, whether literal or from a belt operand, are always relative to the [[Registers|EBB entry point]]. The optional delay serves to synchronize with operations that need to finish before control is transferred to the next EBB. This is particularly important for the predicates to examine for the branch, the value of which is examined after the delay. | The targets in branches, whether literal or from a belt operand, are always relative to the [[Registers|EBB entry point]]. The optional delay serves to synchronize with operations that need to finish before control is transferred to the next EBB. This is particularly important for the predicates to examine for the branch, the value of which is examined after the delay. | ||
Revision as of 20:55, 20 December 2014
Branch on false predicate. There can be several conditionless branches in an EBB and even in the same operation, which are all processed in parallel, but the first successful in the lowest slot wins.
The targets in branches, whether literal or from a belt operand, are always relative to the EBB entry point. The optional delay serves to synchronize with operations that need to finish before control is transferred to the next EBB. This is particularly important for the predicates to examine for the branch, the value of which is examined after the delay.
The branch not taken case is more efficient and faster, i.e. the compiler takes care to schedule the conditional branches with their more likely case not to be taken, to achieve the longest possible code sequences without control transfers.
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
brfl(pred q, p target, lit delay)
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
brfl(pred q, lbl target, lit delay)
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
